Those concerned with the development of signal-controlled electrical devices have long recognized the need to conserve power by temporarily restricting operation of such devices, while retaining the value(s) of such control signal(s) for use when full operation is restored The present invention fulfills this need.
It is often desirable for the user of electronic equipment to have the ability to partially shut down such equipment, such as during periods of relative inactivity, in order to conserve power. Often, such equipment utilizes one or more internally generated or externally provided control signals for controlling some aspect of operation of that equipment. One example of such a control signal is a feedback control signal, such as the voltage or other control in a phase locked loop, or the reference voltage controlling the amount of delay produced by a synchronous delay line. If there is to be a partial shutdown of equipment so controlled, then there will be a need to reduce power to various parts of the system. As a result, the control voltage or other control signal would not be maintained, and so would be lost. If full power is thereafter restored, it will then be necessary to completely redetermine the lost control signal. Particularly if a feedback control signal is involved, such as in a phase-locked loop or in a synchronous delay line, redetermining the lost control signal can require a substantial number of system cycles. As a result, relatively substantial delays can be encountered in such restart of signal-controlled equipment. This situation is made more difficult if the signal or signals involved are analog signals, especially if they were generated by analog circuitry such as an operational amplifier. Such signals are more easily lost, and the static power consumption of an operational amplifier is sufficiently relatively substantial that a partial shutdown would most desirably involve stopping operation of the operational amplifier.
There exist applications in which there is a need to generate multiple internal clock phases or sub phases from a single input clock, all of which are synchronized together, wherein the generated clock signals are corrected for phase and frequency errors, particularly phase errors of integral multiples of 360.degree..
It has been a general practice to employ MOS synchronous delay lines to provide additional timing edges from a reference clock signal. Although such devices have served the purpose, they have not proven entirely satisfactory under all conditions of service because, particularly with larger frequency range requirements, there is a need to correct the outputs of such delay lines for phase not only within a range of 0.degree.-360.degree., but also to correct phase errors which are integral multiples of 360.degree.. Such correction is needed so that the outputs remain relatively in phase with each other.
One such synchronous delay line is described in Bazes, M., "A Novel Precision MOS Synchronous Delay Line" in IEEE Journal of Solid State Circuits, Vol. SC-20, No. 6, December 1985, pp. 1265-1271, which is hereby incorporated by reference. An integrated phase-locked loop including phase detection is described in Johnson, M. G. and Hudson, E. L., "A Variable Delay Line PLL for CPU-Coprocessor Synchronization" in IEEE Journal of Solid State Circuits, Vol. 23, No. 5, October 1988, pp. 1218-1223, which is also hereby incorporated by reference. However, the delay lines, and the phase detectors of Johnson and Hudson, and of Bazes, can be operated over only a limited frequency range, and are subject to start-up or fractional frequency lock-up problems, since a known precision clock input is reguired. If the user needs more flexible clocking requirements, then problems can occur. In Bazes and especially in Johnson and Hudson, the clock waveform input is very controlled and limited to a very small frequency variation. If the user, erroneously or otherwise, would alter the clock frequency in the middle of a cycle, or power the system up and down, then the system of Bazes, and the system of Johnson and Hudson, would likely not operate properly.
Furthermore, in both Bazes and in Johnson and Hudson, if there is a user requirement to substantially reduce power consumption, such that the clock input ceases, then once full power is regained and clock operation is restarted, the system must completely restart as if there had been no previous operation of the system. Such reinitialization of the system introduces delays. This problem is overcome by the present invention.